RTL Design Lead/IC Front-End Architect/Datapath Lead

About the role

You own verification end to end for a first-of-its-kind chiplet. As a founding hire you define the methodology before there's RTL to verify — this role is on the critical path, and getting the coverage strategy and regression infrastructure right early is the single biggest schedule lever we have.

What you'll do

• Front-end micro-architecture and block partitioning; the architecture spec the RTL team builds to
• Front-end design methodology and quality: RTL coding standards, lint, CDC/RDC signoff, and clean-RTL policy across the team
• Transport/link framing/mapping and the adaptation logic
• Timing- and floorplan-aware micro-architecture: pipelining, retiming, and partitioning for physical closure at multi-hundred-Gbps (with the backend team)
• Clocking, reset, and low-power architecture — clock/reset domains, gating strategy, and UPF power intent

What you need

• Verilog
• Any graduate