RTL Engineer Memory Subsystem - Bangalore

About the role

We are looking for a talented RTL Engineer to help build Velaura's next-generation Physical AI SoC, with a focus on the high-speed, low-power memory subsystem that feeds the chip. In this role, you will work closely with architects, performance modelers, software engineers, verification engineers, physical design teams, and memory IP and PHY partners to transform innovative architectural concepts into production silicon.

What you'll do

• Own memory controller and PHY integration, including controller-to-PHY interfaces such as DFI, initialization and training flows, calibration, and bring-up hooks
• Drive high-speed, low-power design of the memory path, including timing closure at high data rates, power-state management such as self-refresh and power-down modes
• Work with software teams to define hardware interfaces, memory maps, execution flows, and performance-critical interactions such as scheduling, prefetching
• Analyze bandwidth, latency, and utilization bottlenecks in the memory path and propose architectural and implementation improvements
• Optimize designs for performance, power, area, scalability, and reliability, including RAS features such as ECC and error reporting in the memory path

What you need

• Verilog
• VLSI
• Calibration
• Any graduate

Good to have

• FPGA
• Machine learning
• Arbitration
• Prototyping