Senior ASIC Design Engineer - NOC IP

About the role

In this position, you will be expected to make architectural trade-offs based on features, performance requirements and system limitations, come up with micro-architecture, implement in RTL, and deliver a fully verified, synthesis/timing clean design. You will work with architects, other designers, pre- and post-silicon verification teams, synthesis, timing and backend teams to accomplish your tasks.

What you'll do

• Own micro-architecture and RTL development of design modules
• Micro-architect features to meet performance, power and area requirements
• Work with HW architects to define critical features
• Collaborate with verification teams to verify the correctness of implemented features
• Co-operate with timing, VLSI and Physical design teams to ensure design meets timing, interface requirements and is routable

What you need

• 7–13 yrs of experience
• VLSI
• Verilog
• FPGA
• Prototyping
• B.Sc

Good to have

• Python
• Perl