Senior Circuit Silicon Correlation DFT Engineer

About the role

Responsible for generating ATPG patterns for Silicon speed path debug. RTL and gate level verification for ATPG, non-ATPG patterns.

What you'll do

• Participate in ground breaking Processor design and debug in deep submicron technologies
• Work in a multi functional team passionate about Silicon characterization and correlation to pre-Silicon Performance and Power models
• Responsible for generating ATPG patterns for Silicon speed path debug

What you need

• Deep learning
• Any graduate