Senior CPU Design Verification Engineer

About the role

We are seeking a Senior CPU Design Verification Engineer to own block‑ and subsystem‑level DV for advanced out‑of‑order (OoO) CPU cores . You will work closely with micro‑architects and RTL designers to verify complex Front end Designs includes branch prediction, Instruction decodes, execution pipelines, memory systems, and coherence protocols using modern, coverage‑driven methodologies.

What you'll do

• Verification Planning & Ownership
• Front‑end: fetch, branch prediction, decode
• Rename and register mapping
• Issue queues / schedulers and execution units
• Load‑store unit (LSU), store buffer, atomics/LR‑SC, fences

What you need

• 5–10 yrs of experience
• UVM
• Verilog
• B.Sc or M.Sc or B.Tech or B.E.