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Senior CPU Formal Verification Engineer

SiFive·Hyderabad

Pay not stated5–9 yrsFull-time

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About the role

We are seeking a Senior Design Formal Verification Engineer to own formal strategies for advanced out‑of‑order (OoO) CPU cores . You will work closely with micro‑architects and RTL designers to verify complex execution pipelines.

What you'll do

  • Identify blocks suitable for applying Formal Verification
  • Create Formal Test-plan for blocks identifying properties to be implemented and sign-off metrics
  • Implementation and maintenance of Formal Verification environments in Chisel
  • Applying various FV techniques to reduce complexity and prove correctness of DUT
  • Debugging RTL to identify causes of failure scenarios

What you need

  • 5–9 yrs of experience
  • Verilog
  • Maintenance
  • Test cases
  • M.Tech or B.Tech or B.E.

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