Senior Design Lead - Design Validation

About the role

Test case development, coding, execution, bug analysis participate in verification closure.

What you'll do

• Has participated in multiple ASIC/SoC verification till tape out stage
• Experience writing ASIC/SoC test plans
• Experience to Build and maintain reusable block-level and sub-system testbenches using System Verilog and the Universal Verification Methodology (UVM)."
• Experience to Write, execute, and debug constrained-random and directed test cases based on defined test plans."
• Experience Set up functional coverage, write system assertions (SVA), and analyze code coverage metrics to identify untested gaps in the design logic

What you need

• 5–10 yrs of experience
• Linux
• Python
• Perl
• Test cases
• UVM
• C
• Any graduate

Good to have

• Verilog