Senior Design Lead - Design Validation

About the role

Test case development, coding, execution, bug analysis

What you'll do

• Has participated in multiple ASIC/SoC verification till tapeout stage
• Experience writing ASIC/SoC testplans
• 2.Experience to Build and maintain reusable block-level and sub-system testbenches using SystemVerilog and the Universal Verification Methodology (UVM)."
• 2.Experience to Write, execute, and debug constrained-random and directed test cases based on defined test plans."
• Experience Set up functional coverage, write system assertions (SVA), and analyze code coverage metrics to identify untested gaps in the design logic

What you need

• UVM
• Verilog
• Perl
• VLSI
• Linux
• Python
• B.Tech or B.E.

Good to have

• Test cases
• C
• Shell scripting