Senior Design Lead

About the role

Clock domain crossings (CDC timing perspective) STA fundamentals (setup/hold, skew, jitter, latency) Experience working with global teams / customers

What you'll do

• Own full-chip STA signoff for all PVT corners and modes (functional, scan, low-power, etc.)
• Drive timing closure at chip level, including setup/hold, noise, OCV/AOCV/POCV
• Analyze and resolve timing violations across hierarchical boundaries
• Define and validate SDC constraints for chip-level integration
• Ensure proper timing budgeting and partitioning across blocks

What you need

• 5–9 yrs of experience
• Python
• Any graduate