Senior Design Lead

About the role

We are looking for hands-on Emulation Engineers to perform pre-silicon validation of complex Design IP using the Synopsys ZeBu emulation platform. The engineer will work on emulation bring-up, test development, regression, functional and performance validation, and debug of Design IP such as PCIe, DDR, Ethernet, MIPI CSI/DSI and other high-speed interfaces.

What you'll do

• Compile and bring up complex Design IP RTL on Synopsys ZeBu
• Configure clocks, resets, interfaces, transactors and emulation IP
• Support RTL compilation, partitioning, mapping and runtime setup
• Develop and maintain IP-level emulation environments
• Integrate ZeBu transactors and protocol solutions

What you need

• 4–8 yrs of experience
• Prototyping
• Verilog
• UVM
• Test cases
• VLSI
• Python
• B.Tech or B.E.

Good to have

• C++
• C
• Perl