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Senior Design Lead

HCLTech·Bengaluru

Pay not stated3–8 yrsFull-time

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About the role

Performs Transmission line & Via modelling and carry out experiments to validate modelling outcomes and methodologies.Deep Understanding of S-parameter & its modelling concepts for Single ended and differential interfaces.Experience in simulating (FD/TD) memory interfaces for Board and Package is required (DDR4/LPDDR4)Experience in simulating (FD/TD) High Speed Serial IO interfaces for Board and Package is required (PCIe Gen3/4, SATA Gen3, USB3/3.1 and Display Interfaces etc.)Good knowledge of…

What you'll do

  • Should be able to analyze and review the layout files related to Signal integrity and Power Integrity problems.Should be able to provide practical solutions to…

What you need

  • 3–8 yrs of experience
  • ANSYS
  • Any graduate

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