Senior Design Lead

HCLTech·Bengaluru

Pay not statedSenior levelFull-time

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About the role

Complete high‑speed LPDDR interface layout (LPDDRx), addressing signal integrity challenges such as skew control, impedance matching, shielding, crosstalk mitigation, and jitter sensitivity in advanced nodes. Foster a culture of knowledge sharing and continuous improvement, contributing to VXL‑compatible layout flows, guidelines, and build reviews that enable first‑silicon success.

What you'll do

Support post‑layout optimization and ECOs, resolving issues related to margin degradation, yield, and manufacturability while maintaining JEDEC compliance
Contribute to PPA optimization with a strong focus on low‑power operation, area efficiency, and reliability requirements specific to LPDDR applications