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Senior Design Lead

HCLTech·Bengaluru

Pay not stated5–7 yrsFull-time
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About the role

Min 5 to 7+ years of FPGA or IP/SoC architecture verification experience Experience working in IP or ARM/RISC-V processor subsystem

What you'll do

  • Able to interface with design and Functional Safety team

What you need

  • 5–7 yrs of experience
  • FPGA
  • FMEA
  • Test cases
  • Perl
  • Python
  • UVM
  • Any graduate

Good to have

  • C

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