Senior Design Lead

About the role

Debug and resolve non-equivalence failures, aborted points, and compare issues due to synthesis, ECO, scan, and DFT logic

What you'll do

• Execute RTL ↔ Netlist, Netlist ↔ Netlist, and ECO FEV at block and full-chip levels
• Create and maintain reference FEV flows and testcases to validate tool features and methodologies
• Develop and automate workflows to improve efficiency and runtime of FEV signoff. Automation using Python/ Perl/Tcl is preferred
• Work closely with RTL, Synthesis, DFT, and Physical Design teams for issue closure
• Generate signoff-ready reports and ensure adherence to project signoff criteria

What you need

• 5–9 yrs of experience
• VLSI
• Any graduate

Good to have

• Python
• Perl