Senior Design Lead

About the role

Candidates with 5 to 7 years experience is mandatory Has participated in multiple ASIC/SoC verification till tapeout stage Full chip TB Architecture definition Experience writing ASIC/SoC testplans 1.Experience in ASIC/SoC Testbench definition 2.Experience to Build and maintain reusable block-level and sub-system testbenches using SystemVerilog and the Universal Verification Methodology (UVM)."

What you'll do

• Test case development, coding, execution, bug analysis
• Participate in verification closure

What you need

• 5–7 yrs of experience
• UVM
• Verilog
• Perl
• Linux
• Python
• Test cases
• B.Tech or B.E.

Good to have

• C
• Shell scripting
• VLSI