Senior Design Lead

About the role

We are seeking a Senior SoC Design Engineer with 7 -10 years of experience in ASIC/SoC design and deep expertise in one or more next-generation compute, memory, interconnect, or coherency technologies. The candidate will be responsible for micro-architecture, RTL design, IP/subsystem development, and SoC integration for complex SoCs used in AI/ML, Datacenter, HPC, Networking, and Server platforms.

What you'll do

• Design and develop RTL for complex ASIC/SoC subsystems using Verilog/SystemVerilog
• Own micro-architecture definition, RTL implementation, and design reviews
• Develop and integrate high-performance IPs, interconnects, memory subsystems, and coherency fabrics
• Collaborate with Architecture, Verification, Physical Design, DFT, Firmware, and Validation teams
• Drive design quality through lint, CDC/RDC, synthesis, and timing closure support

What you need

• 7–10 yrs of experience
• Verilog
• Machine learning
• Python
• Perl
• VLSI
• Any graduate

Good to have

• Prototyping
• FPGA