Senior Design Verification Engineer

About the role

There is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results and for our customers. Energy feeds on energy.

What you'll do

• Develop comprehensive verification plans, clear metrics and continuously measure progress against the plan throughout the project
• Verify design blocks, sub systems and full chip using assertion-based verification, formal verification, directed tests and randomized tests
• Understand the specifications, use cases and develop System Verilog and ‘C’ based testbenches in UVM environment
• Design and develop testbench components such as Universal Verification Components, BFMs and verification tools
• Define and design verification regression environment

What you need

• 6–10 yrs of experience
• FPGA
• Python
• Shell scripting
• Perl
• UVM
• Verilog
• M.Sc or B.Tech or B.E. or B.Sc or BCA or M.Tech or MCA