Senior Design Verification Engineer

About the role

We are seeking a highly skilled and experienced Senior Design Verification Engineer to join our dynamic team. The ideal candidate will possess a strong background in SOC and IP verification, with expertise in Verilog, System Verilog, and UVM. You will play a critical role in ensuring the quality and reliability of our designs through rigorous verification processes.

What you'll do

• Develop and execute comprehensive verification plans for SOC and IP designs
• Utilize Verilog and System Verilog to create and maintain testbenches and verification environments
• Implement UVM-based verification methodologies to enhance the efficiency and effectiveness of the verification process
• Collaborate with design engineers to understand specifications and requirements for various protocols, including AXI, APB, CHI, and USB
• Write and maintain verification code in C/C++ to support advanced verification tasks

What you need

• Verilog
• UVM
• C++
• C
• B.Tech or B.E.