Senior Designer

About the role

Candidates with 3 to 6 years' experience is mandatory Experience to Build and maintain reusable block-level and sub-system testbenches using SystemVerilog and the Universal Verification Methodology (UVM)."

What you'll do

• 2.Experience to Write, execute, and debug constrained-random and directed test cases based on defined test plans
• Experience Set up functional coverage, write system assertions (SVA), and analyze code coverage metrics to identify untested gaps in the design logic
• 3.Debug complex simulation failures using waveform viewer tools to isolate design bugs from testbench issues
• Experince in SOC C based tests coding & debugging"

What you need

• 3–6 yrs of experience
• Python
• UVM
• Verilog
• Linux
• Perl
• Test cases
• Any graduate

Good to have

• C