Senior Designer

About the role

We are seeking a Memory Timing & Power Characterization Engineer responsible for detailed analysis, modeling, and validation of timing and power characteristics of embedded memory/IPs (SRAM, NVM, etc.) . The role involves working closely with design, circuit, PDK, and product teams to ensure high-performance and low-power memory solutions across PVT corners.

What you'll do

• Perform timing characterization (setup/hold, access time, cycle time, pulse widths) for memory IPs
• Generate and validate timing models (.lib, CCS) across all corners (PVT variations)
• Perform path analysis and debugging for timing failures
• Support STA teams with accurate timing models and insights
• Perform dynamic and leakage power characterization

What you need

• 3–5 yrs of experience
• Python
• Shell scripting
• Perl
• Any graduate