Senior Digital Verification Engineer

About the role

DV engineers collaborate closely with RTL design, architecture modeling, custom analog IP, compiler, emulation, and post-silicon teams to ensure the full system operates as intended.

What you'll do

• Collaborate with RTL designers and architects to verify subsystems such as scheduling fabrics, interconnects, DMA engines, and memory controllers

What you need

• 5–9 yrs of experience
• UVM
• Verilog
• Python
• Test cases
• B.Tech or B.E. or PhD