Senior Engineer - ASIC Verification

About the role

Develop verification testbench components for chip/module level using System Verilog, C/C++. Use Verification methodologies (Object oriented, UVM etc) to develop extendable test-bench/test-cases environment. Define and execute detailed verification plan from spec working with architects, designers, system engineers.

What you'll do

• Develop verification testbench components for chip/module level using System Verilog, C/C++
• Use Verification methodologies (Object oriented, UVM etc) to develop extendable test-bench/test-cases environment
• Define and execute detailed verification plan from spec working with architects, designers, system engineers
• Write tests, Debug tests, automate regression scripts and regression environment

What you need

• 4–8 yrs of experience
• Verilog
• UVM
• C++
• C
• Test cases
• Perl
• Any graduate