Senior Engineer- Clock Planning- PD-Full Chip/Sub system

About the role

Drive full-chip clock architecture and planning, ensuring scalable distribution, timing robustness, implementation feasibility, and cross-hierarchy convergence.

What you'll do

• Define clock planning strategy and distribution architecture
• Own clock source, hierarchy, partition, and interface planning
• Drive skew, latency, transition, and clock QoR targets
• Coordinate with PnR, STA, RTL, DFT, and integration teams
• Lead technical reviews, risk management, and clock closure

What you need

• 5–7 yrs of experience
• B.Tech or B.E. or M.Tech

Good to have

• Python