Senior Engineer, Design Verification (MCU)

About the role

Be a part of end‑to‑end verification execution for SOC owning complex digital IP’s and subsystems from specification to sign‑off

What you'll do

• Define and drive IP‑level verification strategies, including test plans, coverage models, and closure criteria
• Develop scalable, reusable UVM‑based verification environments for IP and subsystem verification
• Lead functional, code, assertion, and cross‑coverage closure, ensuring high‑quality sign‑off with clear metrics
• Drive constraint random and directed test methodologies for thorough protocol, corner‑case, and stress verification
• Collaborate with RTL, Architecture, Emulation, and SoC Verification teams to ensure seamless IP integration

What you need

• 2–4 yrs of experience
• UVM
• Embedded C
• Verilog
• C++
• C
• Python
• B.Tech or B.E.

Good to have

• Machine learning
• Shell scripting
• Perl
• Test cases