Senior Engineer - Design Verification

About the role

This is a T3 / Senior Engineer individual-contributor role within the Interconnect horizontal area, focused on coherent interconnect and related subsystem behavior. In this role, you will work across architecture, RTL, formal, and design verification teams to verify coherent data movement, protocol correctness, ordering, flow control, quality-of-service behavior, and subsystem integration across multiple interface types and bridge paths.

What you'll do

• Understand the coherent interconnect architecture and create effective verification strategies and test plans for the assigned area
• Develop and maintain verification environments, checkers, scoreboards, assertions, stimulus, and coverage models for coherent traffic, ordering rules, backpressure
• Verify subsystem behavior across interface boundaries, protocol adaptation layers, and bridge paths, including conversion, buffering, deinterleaving
• Define and execute directed and constrained-random tests that expose corner cases in coherency, concurrency, ordering, credits, arbitration, QoS behavior
• Analyze failures, isolate root cause, and drive fixes across RTL, assertions, testbench infrastructure, and test content

What you need

• 5–9 yrs of experience
• UVM
• Verilog
• Test cases
• Arbitration
• B.Tech or B.E.

Good to have

• FPGA
• Python