senior engineer- DV

About the role

senior engineer- DV at Quest Global. Knowledge of Code coverage using features in existing simulators or stand-alone tools like Surecov, HDL score etc.

What you'll do

• Working on full chip verification and OVM/UVM Methodology, System Verilog is a must with 3+years of recent work experience, worked on passing test cases, test benches
• Should be ARM based SoC verification only. No need to mention tools
• Experience level 3 to 5 years
• Good in concepts Code coverage and functional coverage
• Expertise in Verilog and / or VHDL is desired

What you need

• 3–5 yrs of experience
• Python
• C++
• Verilog
• UVM
• Linux
• Test cases
• B.Tech or B.E. or M.Tech

Good to have

• Perl