Senior Engineer - Emulation

About the role

Execute and own FPGA prototyping and emulation activities for complex SoC designs, with primary focus on multi-FPGA prototyping, synthesis/P&R, timing closure, bitfile generation, board bring-up and system-level debug. Support emulator model bring-up on ZeBu/Veloce and collaborate with Design, DV, Firmware and Board teams to resolve issues.

What you'll do

• Execute end-to-end FPGA prototyping and emulation activities for SoC/ASIC designs, covering RTL preparation, synthesis, partitioning, P&R, bitfile generation
• Take ownership of FPGA prototype model bring-up on platforms such as HAPS, Protium and other FPGA-based prototyping systems
• Support multi-FPGA partitioning and implementation, including partition optimization, FPGA resource utilization, inter-FPGA connectivity
• Perform FPGA synthesis, P&R and timing analysis, identify implementation bottlenecks and work on resolving timing violations, congestion and resource issues
• Support clock and reset implementation for FPGA prototypes, including analysis of ASIC clock structures and development/application of appropriate FPGA constraints

What you need

• FPGA
• Prototyping
• Perl
• Python
• B.Tech or B.E.