Senior Engineer IP Verification - Digital Design Verification

About the role

Understand design specifications and define verification scope, strategy, and plans for block/chip RTL verification Develop, execute, and maintain verification testbenches and test vectors using digital simulation tools and methodologies (SV-UVM) Run directed and constrained-random tests and regressions; analyze results and triage failures.

What you'll do

• Develop, execute, and maintain verification testbenches and test vectors using digital simulation tools and methodologies (SV-UVM)
• Run directed and constrained-random tests and regressions; analyze results and triage failures
• Close verification metrics (functional coverage / code coverage as applicable) and identify verification holes to demonstrate readiness toward tapeout
• Provide verification support to design projects by simulating, analyzing
• Develop and maintain test benches and test vectors using simulation tools and run regressions for coverage analysis and improvements

What you need

• 4–6 yrs of experience
• UVM
• Python
• Test cases
• Perl
• B.Tech or B.E.