Senior Engineer -Low Power CLP

About the role

If your interested in working with a team of collaborative and smart engineers responsible for validating RTL-to-Gate and Gate-to-GDS implementations, ensuring power intent correctness, and enabling high-quality silicon tapeout

What you'll do

• Low Power structural check
• Perform low-power verification using Cadence Conformal Low Power (CLP) or Synopsys VCLP
• Verify and validate UPF implementation across RTL, netlist, and physical design stages
• Perform power-aware equivalence checking and resolve identified issues
• Analyze, debug, and resolve CLP structural, rule-based, and power-aware verification failures

What you need

• 5–9 yrs of experience
• Python
• VLSI
• Perl
• Verilog
• Travel booking
• Any graduate