Senior Engineer - Physical design

About the role

If your interested in working with a team of collaborative and smart engineers responsible for validating RTL-to-Gate and Gate-to-GDS implementations, ensuring power intent correctness, and enabling high-quality silicon tapeout

What you'll do

• Develop and deploy new methodologies to improve implementation efficiency and results
• Support and develop detailed implementation analysis and data-mining methodologies
• Automation , Python knowledge and bringing in faster and efficient execution
• Work with implementation and physical IP RTL design teams to drive analysis and optimization of our IP
• LEC, CLP and ECO implementation knowledge to handle ECO cycles

What you need

• 8–14 yrs of experience
• VLSI
• Verilog
• Python
• Travel booking
• Perl
• B.Tech or B.E.