Senior Engineer, Physical Design - Interconnects

About the role

As a Senior Physical Design Engineer (Interconnects) , you will be responsible for the physical design implementation of the high-speed logic that binds the SoC together. This includes scalable Network-on-Chips (NoC), coherent CPU clusters, and critical Uncore subsystems. In this role, you will move beyond standard block-level implementation to tackle the unique challenges of high-speed Interconnects.

What you'll do

• Move beyond standard block-level implementation to tackle the unique challenges of high-speed Interconnects
• Shape the Ecosystem: Help build the RISC-V infrastructure that is redefining the global compute landscape

What you need

• 4–7 yrs of experience
• VLSI
• Budgeting
• M.Sc or B.Tech or B.E.