Senior Engineer - PV/EMIR

About the role

We are looking for an experienced Lead Engineer - Physical Verification to drive signoff-quality physical verification for advanced-node ASIC/SoC designs. The candidate will be responsible for DRC, LVS, ERC, Antenna, Density, and Physical Verification closure while collaborating with Physical Design, Layout, Foundry, and CAD teams.

What you'll do

• Lead block-level and full-chip Physical Verification activities
• Design Rule Check (DRC)
• Layout vs Schematic (LVS)
• Electrical Rule Check (ERC)
• Analyze and resolve physical verification violations to achieve signoff

What you need

• VLSI
• Any graduate