Senior Engineer, SoC PnP Architect

About the role

Performance analysis using cycle-accurate, transaction-level, and emulation-based environments Waveform-based debug and signal-level performance analysis Latency, bandwidth, throughput, QoS, and utilization characterization Transaction-level tracing and protocol debug across CHI, AXI, PCIe, CXL, or equivalent system protocols

What you'll do

• Building and calibrating models for performance, power, latency, bandwidth, utilization, and efficiency analysis
• Using models to guide SoC architecture decisions, IP configuration, memory/interconnect sizing, QoS strategy, and platform-level optimization
• Drive data-based architectural recommendations
• Influence SoC architecture, platform configuration, and product-level PnP decisions
• Lead investigations across multiple teams and convert debug findings into architectural improvements, tuning proposals, or product guidance

What you need

• 4–7 yrs of experience
• Python
• C++
• Linux
• Root cause analysis
• C
• Any graduate