Senior Engineer - STA & Synthesis

About the role

Execute synthesis and static timing analysis activities, supporting constraint development, timing debug, optimization, and signoff closure.

What you'll do

• Run synthesis and STA across modes and corners
• Develop, validate, and maintain SDC constraints
• Debug timing violations and constraint issues
• Support timing ECO generation and implementation
• Track QoR and prepare closure reports

What you need

• 5–8 yrs of experience
• VLSI
• B.Tech or B.E. or M.Tech

Good to have

• Python
• Perl