Senior Engineer Verification

About the role

Senior Engineer Verification at Infineon. Key responsibilities in your new role.

What you'll do

• Key responsibilities in your new role
• Take responsibility of developing SV RNM models and its verification against schematic
• Gain knowledge on AMS methodologies/Simulators
• Take responsibility of analog vectors (test parameters) verification at SoC level using DMS verification flow involving UVM testbench and RNM models

What you need

• Circuit design
• UVM
• Python
• Customer success
• Perl
• Any graduate