Senior Formal Verification Engineer - Bangalore

About the role

We are looking for a talented Senior Formal Verification Engineer to define, own, and scale the formal verification effort that hardens Velaura's next-generation Physical AI SoC. You will apply formal methods to the hardest correctness problems in the design, working with architects, RTL, and verification teams to prove correctness exhaustively and reach coverage that simulation cannot.

What you'll do

• Own and drive formal verification for complex SoC blocks—CPUs, control processors, floating-point units, vector/SIMD engines, and datapath-heavy designs
• Write high-quality SVA properties and formal testbenches to prove functional correctness, including end-to-end and datapath-equivalence checks
• Apply full proofs, bounded model checking, assume-guarantee reasoning, and abstraction to close proofs on deep-state designs
• Debug counterexamples and drive convergence on hard proofs using abstraction, constraints, and decomposition
• Verify floating-point and arithmetic units for IEEE-754 compliance using formal datapath and equivalence checking

What you need

• 10–18 yrs of experience
• Verilog
• Any graduate

Good to have

• C++
• C
• Machine learning