Senior Formal Verification Engineer

About the role

In this position, you will be the dedicated formal expert for the VU team, responsible for designing scalable formal testbenches, writing mathematical properties, and ensuring the absolute algorithmic and architectural integrity of our vector pipeline. You will work side-by-side with VU microarchitects to hunt down deep corner-case bugs and achieve formal sign-off on high-complexity arithmetic and execution blocks.

What you'll do

• Block-Level Execution & Convergence Engineering (90%)
• End-to-End Testbench Ownership: Design, deploy, and maintain robust formal verification environments for complex Vector Unit sub-blocks (e.g.
• Datapath & Arithmetic Verification: Implement advanced word-level modeling, bit-blasting
• Embedded Mentorship & Best Practices (10%)

What you need

• 5–9 yrs of experience
• Verilog
• Python
• Structural design
• Bash
• PhD