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Senior FPGA Design Engineer

Tudip Technologies·Pune

Pay not stated8–14 yrsFull-time

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About the role

We are seeking a highly skilled FPGA Design Engineer with expertise in L2 Ethernet Switching RTL to join our dynamic team. In this role, you will be responsible for designing, implementing, and verifying FPGA-based solutions for Layer 2 (L2) Ethernet switching functionalities. The ideal candidate will have a strong background in FPGA design, RTL coding, and Ethernet protocols, along with a passion for pushing the boundaries of technology.

What you'll do

  • Design and develop FPGA-based solutions for Layer 2 Ethernet switching functionalities, including VLAN tagging, frame forwarding, MAC address learning
  • Implement RTL code for Ethernet switch features using Verilog or VHDL, ensuring high performance and low latency
  • Collaborate with cross-functional teams including hardware engineers, software engineers, and system architects to define system requirements and interface specifications
  • Conduct RTL simulation and verification to ensure functional correctness and adherence to design specifications
  • Optimize FPGA designs for area, power, and performance metrics, considering constraints such as resource utilization and timing closure

What you need

  • 8–14 yrs of experience
  • FPGA
  • Verilog
  • Test cases
  • B.Tech or B.E.

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