Senior FPGA IP Design Engineer

About the role

We are seeking a Senior FPGA Soft IP Development Engineer to own the architecture, micro-architecture, and parameterizable RTL design of high-performance soft intellectual property (IP) blocks. In this role, you will be responsible for developing critical system-level IP cores—including advanced AMBA AXI Interconnect IP - ensuring their portability, scalability, and timing closure across diverse FPGA architectures.

What you'll do

• Own micro-architecture definition and RTL design for critical blocks such as schedulers, command pipelines, coherency/ordering logic, and system interfaces
• Collaborate closely with the verification team to shape test plans and improve verification coverage
• Work with the physical design team to understand and resolve timing, power, and congestion challenges
• Work with the verification team on regression failure debug and root cause, and provide RTL fixes if necessary
• Provide technical support to the FAE team on pre-sales customer engagements

What you need

• 5–9 yrs of experience
• FPGA
• Python
• Test automation
• Perl
• Verilog
• VLSI
• B.Tech or B.E.

Good to have

• Test cases
• IPR