Senior Group Technical Architect

About the role

The Silicon Design Verification Manager is responsible for leading pre‑silicon verification of complex IP, subsystem, and SoC designs , ensuring functional correctness, coverage closure, schedule adherence, and strong customer alignment. The role combines technical depth, customer engagement, team leadership, and delivery governance across large‑scale SoC programs.

What you'll do

• Program & Delivery Ownership
• Own end‑to‑end DV delivery for IP / Subsystem / SoC‑level verification programs
• Drive verification planning, execution, coverage closure, and sign‑off aligned to customer milestones
• Ensure monthly and sprint‑wise planning , risk identification, dependency tracking, and mitigation
• Accountable for schedule, quality, and billing health , preventing leakage and delivery surprises

What you need

• 15–27 yrs of experience
• UVM
• Talent management
• LLMs
• Verilog
• B.Tech or B.E.