Senior IC Packaging Engineer

About the role

This role is designed for a senior technologist who combines deep hands-on expertise with system-level thinking, and who thrives in high-ambiguity, high-impact settings. You will define and drive high-performance, low-power packaging architectures spanning 2D and RDL based fan-out (2.5D), chiplet-based designs, and heterogeneous integration, leading efforts from early technology path finding through production ramp.

What you'll do

• Serve as technical authority for IC and SiP packaging across multiple products and programs
• Own package architecture and technology roadmap, aligned with product, cost, and scalability goals
• Lead chiplet-based packaging strategies, including UCIe, silicon interposers, and advanced RDL
• Perform and guide hands-on package design and physical layout, including critical structures for High-speed SerDes/PHY (PCIe, CXL), LPDDR5, UCIe
• Define substrate stack-ups, materials, bump/RDL architectures, and DFM guidelines for advanced nodes

What you need

• 10–18 yrs of experience
• Roadmapping
• PhD

Good to have

• ANSYS