Senior Lead Engineer - DV

About the role

We are looking for a highly skilled and hands on Lead Engineer to lead and drive Subsystem/SOC Design Verification for an ARM based SoC Design. Extensive experience in SV/UVM based SOC or IP Verification.

What you'll do

• Own and delivery IP/Subsystem/SOC Testbench development, define Test plan, Test development & debug
• Strong knowledge in CPU based SOC architecture
• Develop and execute System Verilog/UVM Testbenches for SOC/IP Verification
• Develop SV/UVM based SOC/IP Testbench & Implement and run directed, random, and constrained random tests
• Analyze & Debug simulation failures across IP, interconnects , Subsystem & Top level, and work with RTL team for resolution

What you need

• 5–9 yrs of experience
• UVM
• Python
• Perl
• Test cases
• Verilog
• Any graduate