Senior Lead Engineer – Memory design

About the role

We are seeking a Lead Memory Design Engineer to join NXP’s NVM IP design group in Bangalore, India. This role involves leading and managing a diverse NVM IP portfolio, developing and maintaining automated IP management solutions, and collaborating with third-party NVM IP vendors and NXP product design teams to deliver high-quality, scalable NVM IP solutions across multiple business verticals.

What you'll do

• As the Senior NVM IP Lead Engineer for our newly formed Bangalore team, you will be part of a Global NVM design department
• Be leading the NVM IP benchmarking, onboarding, release and support competence for a wide 3rd-party NVM and NXP-proprietary IP platform including Logic-NVM, Flash
• NVM IP benchmarking for a given product and technology requirements
• Execute IP onboarding (IP design kit preparation and verification) and release to product team
• Support product design teams with NVM IP integration and troubleshooting

What you need

• 7–13 yrs of experience
• Circuit design
• Travel booking
• Troubleshooting
• M.Sc or B.Tech or B.E.