Senior Lead Engineer

About the role

a)Lead full-chip timing closure, driving convergence to performance, power, and tapeout targets across the design hierarchy. b)Provide technical leadership in STA, timing analysis, constraint validation, and cross-functional issue resolution. c)Drive execution excellence through risk management, schedule tracking, and collaboration with IP, PD, RTL, and methodology teams.

What you'll do

• Perform STA and timing closure
• FCT ECO generation/Interface timing closure
• Exposure to Innovus / Fusion Compiler

What you need

• 6–10 yrs of experience
• B.Tech or B.E. or M.Tech

Good to have

• Python