Senior Lead Engineer - STA

About the role

The Digital Physical Design Engineer is responsible for complete STA signoff for the SOC or Subsystem. The individual is responsible for writing timing constraints, interacting with the counterpart functions, such as Frontend, DFT and IP to write correct constraints, refining constraints throughout SOC design cycle and constraints validation.

What you'll do

• Responsible for complete STA signoff for the SOC or Subsystem
• Responsible for writing timing constraints, interacting with the counterpart functions, such as Frontend, DFT and IP to write correct constraints
• Responsible for complete timing signoff till the tapeout for subsystem or full chip

What you need

• VLSI
• Any graduate