Senior Lead

About the role

We are looking for an experienced DV / DFx Verification Engineer to work on verification of Design-for-Test (DFT) and Design-for-Debug (DFD) features for complex AMD SoCs. The engineer will be responsible for developing verification plans, building SystemVerilog/UVM-based environments, creating tests, debugging regressions and driving coverage closure across IP, subsystem and SoC levels.

What you'll do

• Develop and execute DFx verification test plans based on architecture and design specifications
• Verify DFx features at IP, subsystem and SoC levels
• Develop SystemVerilog/UVM testbenches, sequences, checkers, scoreboards, monitors and coverage models
• Develop directed and constrained-random tests for DFx features
• On-chip debug / trace / observability

What you need

• Verilog
• UVM
• Python
• Root cause analysis
• Perl
• Ruby
• B.Tech or B.E.

Good to have

• C++
• C
• Prototyping
• FPGA
• Test cases