Senior Manager ASIC Verification

About the role

The Senior Manager of digital design and digital verification leads a team responsible for designing/verifying complex mixed-signal ICs that integrate Analog & digital components. This role demands deep technical expertise, strategic leadership, and cross-functional collaboration to ensure first-pass silicon success

What you'll do

• Responsible for designing/verifying complex mixed-signal ICs that integrate Analog & digital components
• Develop testbenches using System Verilog and UVM for functional and power aware RTL
• Develop UVM component like agents (active and passive), scoreboards and environment etc., Develop assertions, functional coverage
• Develop test plan, UVM based test sequences, layered sequences, virtual sequencers
• Drive closure of verification metrics to cover verification space. Work with the team to identify and close gaps in functional

What you need

• 10–18 yrs of experience
• UVM
• Verilog
• Python
• Test cases
• Customer success
• Perl
• PhD