Senior Memory Mask Design Engineer

About the role

We are looking for a Senior Digital/Memory Mask Design Engineer – someone who is excited to join a growing group of diverse individuals responsible for handling challenging high-speed digital memory circuit designs. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel.

What you'll do

• Implement IC layout of innovative, high-performance, high-speed CMOS integrated circuits in foundry CMOS process nodes in 3nm,5nm
• Lead the architecture and layout design of key memory subsystems, including control logic, sense amplifiers, I/O blocks, bit-cell arrays
• Direct custom layout and verification of complex memory cells, setting standards and methodologies for compiler-driven design flows
• Be responsible for and optimize all physical verification activities, including DRC, LVS, density analysis, and comprehensive tape-out checks
• Drive the identification and resolution of complex physical design issues in compiler-generated layouts, mentoring junior engineers in established methodologies

What you need

• 6–11 yrs of experience
• VLSI
• B.Tech or B.E. or M.Tech