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Senior PD Engineer - STA & Timing Closure

AMD·Hyderabad

Pay not stated8–10 yrsFull-time

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About the role

The focus of this role is to plan and execute full chip timing activities and signoff for advanced chiplets in latest technologies. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.

What you need

  • 8–10 yrs of experience
  • VLSI
  • Perl
  • B.Tech or B.E. or M.Tech

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