Senior Principal Design Verification Engineer

About the role

We are seeking an experienced Senior Principal Design Verification Engineer to lead verification of complex SoC, IP, and modem subsystem designs. This role requires deep technical expertise, strong leadership, and the ability to influence architecture, methodology, and verification strategy across global engineering organizations.

What you'll do

• Own verification strategy, planning, execution, and signoff for complex SoC/IP and modem programs
• Architect scalable and reusable SystemVerilog/UVM verification environments
• Develop verification plans, coverage models, assertions, scoreboards, and checking methodologies
• Drive coverage closure and verification signoff using data-driven quality metrics
• Debug complex design and verification issues and drive root-cause resolution across teams

What you need

• 12–22 yrs of experience
• UVM
• Verilog
• Python
• Root cause analysis
• Perl
• B.Tech or B.E. or M.Tech